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4-Layer PCB Stackup Design: Complete Guidelines for Optimal Performance

Jason Chu
Product Manager
April 5, 2024
Post Views: 136

Four copper layers allow a 4-layer PCB stackup to balance routing, reference planes, power distribution, signal integrity, and manufacturability. For instance, many general-purpose and moderately high-speed designs use Top Signal / Ground Plane / Power Plane / Bottom Signal as a practical starting arrangement, with critical top-layer signals referenced to the adjacent ground plane.

However, the final construction still depends on controlled-impedance targets, finished copper, board thickness, component density, EMC and power requirements, laminate selection, and fabrication capability. Accordingly, this guide covers layer order, reference-plane design, impedance geometry, standard 4-layer constructions, heavy copper, prepreg, and the manufacturing variables that should be confirmed before routing or production release.

Structure and Layer Functions

A 4-layer PCB contains four conductive copper layers separated by laminate core and prepreg. For example, a common construction assigns the internal layers to ground and power while keeping the outer layers available for components and routing.

Layer	Typical Function	Design Purpose
L1	Top Signal / Components	Components and critical routing
L2	Ground Plane	Continuous signal reference and return path
L3	Power Plane	Power distribution and selected low-risk routing
L4	Bottom Signal	Secondary routing and components

Compared with a 2-layer PCB, dedicated internal planes can improve return-path continuity, reduce loop area, simplify power distribution, and make controlled-impedance routing more practical. These benefits depend on layout quality; adding two layers alone does not correct poor reference-plane design.

Recommended 4-Layer PCB Layer Order

Option A

Signal / Ground / Power / Signal

Practical starting point for many general-purpose designs.

Option B

Ground / Signal / Signal-Power / Ground

Consider for EMC-sensitive designs where outer ground layers are useful.

Consider 6+ Layers

Dense / High-Speed / Multi-Domain

Use more layers when four layers cannot preserve routing and reference-plane margin.

If routing density, high-speed interfaces, or reference-plane requirements exceed a practical four-layer architecture, consider moving beyond four layers. In that case, review WellerPCB’s 6-layer PCB stackup design options.

Reference Planes and Signal Integrity in a 4-Layer PCB

Optimized 4-layer PCB stackup for signal integrity, power integrity and reference plane design — An optimized 4-layer stackup keeps critical signals closely referenced to a continuous plane.

High-frequency return current follows the electromagnetic return path associated with the signal and its reference plane. Accordingly, for L1 routing, a continuous L2 ground plane gives critical signals a predictable reference and helps minimize return-loop area.

Avoid routing high-speed traces over plane splits, large voids, or slots. A trace can retain the same physical width and still encounter an impedance discontinuity when its reference environment changes. Likewise, when a signal changes layers, review the return-current transition and provide stitching vias or another appropriate return structure where required.

Controlled Impedance in a 4-Layer PCB Stackup

Specifically, controlled impedance depends on the complete transmission-line geometry: trace width, finished copper thickness, dielectric height to the reference plane, material Dk, solder mask, differential-pair spacing, and etched conductor profile.

Impedance Design Risk

A 50Ω trace has no universal width. Trace geometry must be calculated from the actual dielectric height, finished copper, material properties, and approved production stackup.

Consequently, use the production stackup approved by the PCB manufacturer for impedance calculations. WellerPCB’s PCB controlled impedance guide covers the relationship between stackup geometry, calculation, manufacturing variation, and verification.

For additional industry guidance, see the IPC-2141A controlled-impedance design guide.

WellerPCB 4-Layer PCB Stackup Thickness Options

4-layer PCB foil lamination stackup with copper foil, prepreg and inner core construction — Typical 4-layer foil construction uses outer copper foil, prepreg and an inner laminate core.

In addition, WellerPCB supports multiple finished thicknesses for standard 4-layer FR-4 constructions. These values are production references rather than universal impedance stackups. Material, copper weight, dielectric geometry, and impedance requirements should be confirmed for the actual PCB build.

4L PCB Stack-Up T=0.50mm

	Layer			T: um	Material
SMT		Soldermask		20	Solder rmask
TOP	1	Copper		18-25	Copper plating
				18	Base copper
		Prepreg	2116X1	105	Prepreg
INT1	2	Copper		35	Copper
		Core	FR4	130	Core

INT2	3	Copper		35	Copper
		Prepreg	2116X1	105	Prepreg
BOT	4	Copper		18	Base copper
				18-25	Copper plating
SMB		Soldermask		20	Solder rmask
	Finished PCB thickness: 0.5+/-0.10mm

4L PCB Stack-Up T=0.80mm

	Layer			T: um	Material
SMT		Soldermask		20	Solder rmask
TOP	1	Copper		18-25	Copper plating
				18	Base copper
		Prepreg	1080X1		Prepreg
			7628X1
INT1	2	Copper		35	Copper
		Core	FR4	175	Core

INT2	3	Copper		35	Copper
		Prepreg	7628X1		Prepreg
			1080X1
BOT	4	Copper		18	Base copper
				18-25	Copper plating
SMB		Soldermask		20	Solder rmask
	Finished PCB thickness: 0.8+/-0.10mm

4L PCB Stack-Up T=1.00mm

	Layer			T: um	Material
SMT		Soldermask		20	Solder rmask
TOP	1	Copper		18-25	Copper plating
				18	Base copper
		Prepreg	1080X1		Prepreg
			7628X1
INT1	2	Copper		35	Copper
		Core	FR4	440	Core

INT2	3	Copper		35	Copper
		Prepreg	7628X1		Prepreg
			1080X1
BOT	4	Copper		18	Base copper
				18-25	Copper plating
SMB		Soldermask		20	Solder rmask
	Finished PCB thickness: 1.00+/-0.10mm

4L PCB Stack-Up T=1.60mm

	Layer			T: um	Material
SMT		Soldermask		20	Solder rmask
TOP	1	Copper		18-25	Copper plating
				18	Base copper
		Prepreg	1080X1		Prepreg
			7628X1
INT1	2	Copper		35	Copper
		Core	FR4	930	Core

INT2	3	Copper		35	Copper
		Prepreg	7628X1		Prepreg
			1080X1
BOT	4	Copper		18	Base copper
				18-25	Copper plating
SMB		Soldermask		20	Solder rmask
	Finished PCB thickness: 1.60+/-0.16mm

4L PCB Stack-Up T=2.00mm

	Layer			T: um	Material
SMT		Soldermask		20	Solder rmask
TOP	1	Copper		18-25	Copper plating
				18	Base copper
		Prepreg	1080X1		Prepreg
			7628X1
INT1	2	Copper		35	Copper
		Core	FR4	1530	Core

INT2	3	Copper		35	Copper
		Prepreg	7628X1		Prepreg
			1080X1
BOT	4	Copper		18	Base copper
				18-25	Copper plating
SMB		Soldermask		20	Solder rmask
	Finished PCB thickness: 2.00+/-0.20mm

4L PCB Stack-Up T=2.50mm

	Layer			T: um	Material
SMT		Soldermask		20	Solder rmask
TOP	1	Copper		18-25	Copper plating
				18	Base copper
		Prepreg	1080X1		Prepreg
			7628X1
INT1	2	Copper		35	Copper
		Core	FR4	1930	Core

INT2	3	Copper		35	Copper
		Prepreg	7628X1		Prepreg
			1080X1
BOT	4	Copper		18	Base copper
				18-25	Copper plating
SMB		Soldermask		20	Solder rmask
	Finished PCB thickness: 2.50+/-0.25mm

4L PCB Stack-Up T=3.00mm

	Layer			T: um	Material
SMT		Soldermask		20	Solder rmask
TOP	1	Copper		18-25	Copper plating
				18	Base copper
		Prepreg	1080X1		Prepreg
			7628X1
INT1	2	Copper		35	Copper
		Core	FR4	2330	Core

INT2	3	Copper		35	Copper
		Prepreg	7628X1		Prepreg
			1080X1
BOT	4	Copper		18	Base copper
				18-25	Copper plating
SMB		Soldermask		20	Solder rmask
	Finished PCB thickness: 3.00+/-0.30mm

Heavy-Copper 4-Layer PCB Stackup

4-layer heavy copper PCB stackup design for 2 oz copper and multilayer lamination — Heavy-copper stackups require additional attention to resin filling, etching and lamination.

Moreover, higher copper weights affect etching, minimum trace/space capability, resin filling, lamination, and impedance geometry. Furthermore, the prepreg construction must provide sufficient resin around the copper pattern while maintaining the required finished thickness and structural reliability. For additional process limits, see the heavy copper PCB manufacturing guide.

4L PCB Stack-Up T=1.60mm, 2/2/2/2oz, Option-1

	Layer			T: um	Material
SMT		Soldermask		20	Solder rmask
TOP	1	Copper		25-35	Copper plating
				35	Base copper
Not the best option		Prepreg	7628X1		Prepreg
			7628HX1
INT1	2	Copper		70	Copper
		Core	FR4	460	Core

INT2	3	Copper		70	Copper
Not the best option		Prepreg	7628HX1		Prepreg
			7628X1
BOT	4	Copper		35	Base copper
				25-35	Copper plating
SMB		Soldermask		20	Solder rmask
	Finished PCB thickness: 1.60+/-0.16mm

4L PCB Stack-Up T=1.60mm, 2/2/2/2oz, Option-2

	Layer			T: um	Material
SMT		Soldermask		20	Solder rmask
TOP	1	Copper		25-35	Copper plating
				35	Base copper
The best option		Prepreg	1080 (RC 60%)	76	Prepreg
			7628 (RC 48%)	220
INT1	2	Copper		70	Copper
		Core	FR4	830	Core

INT2	3	Copper		70	Copper
The best option		Prepreg	7628 (RC 48%)	220	Prepreg
			1080 (RC 60%)	76
BOT	4	Copper		35	Base copper
				25-35	Copper plating
SMB		Soldermask		20	Solder rmask
	Finished PCB thickness: 1.60+/-0.16mm

By contrast, the preferred example uses a more favorable prepreg and resin arrangement for lamination. This shows why stackup engineering cannot rely on adding nominal material thicknesses alone. Copper pattern density, resin content, and press behavior also affect the finished construction.

Prepreg, Resin Content, and Dielectric Constant

PCB prepreg selection guide for multilayer stackup design, resin content and dielectric thickness — Glass style and resin content influence pressed dielectric thickness, lamination behavior, and impedance modeling.

First, during multilayer lamination, prepreg forms the bonding dielectric. Its final pressed thickness depends on glass style, resin content, copper thickness, copper pattern, and lamination conditions. As a result, common constructions such as 1080, 2116, and 7628 should not be assumed to have identical physical or electrical behavior.

Thus, a single value such as “FR-4 Dk = 4.4” should not be treated as universal production data. WellerPCB’s prepreg Dk selection guide explains how dielectric data should be applied to PCB stackup and impedance work.

Based Material Line Up S1000H (S1000HB)-PREPREG (B-STAGE)

Glass style	RC (%) Nominal	Thickness		Dk				Df
Glass style	RC (%) Nominal	mm	mil	1GHz	3GHz	5GHz	10GHz	1 GHz	3 GHz	5 GHz	10 GHz
7628	43*	0.185	7.28	4.81	4.74	4.74	4.73	0.014	0.015	0.015	0.016
7628	46	0.195	7.68	4.74	4.68	4.66	4.66	0.015	0.016	0.016	0.016
7628	48	0.205	8.07	4.70	4.63	4.61	4.61	0.015	0.016	0.016	0.017
7628	50	0.215	8.46	4.65	4.58	4.57	4.57	0.016	0.016	0.017	0.017
7628	52	0.225	8.86	4.59	4.52	4.51	4.50	0.016	0.016	0.017	0.017
1506	48	0.160	6.30	4.70	4.63	4.61	4.61	0.015	0.016	0.016	0.017
1506	50	0.170	6.69	4.65	4.58	4.57	4.57	0.016	0.016	0.017	0.017
1506	52	0.180	7.09	4.59	4.52	4.51	4.50	0.016	0.016	0.017	0.017
2116	52*	0.113	4.45	4.59	4.52	4.51	4.50	0.016	0.016	0.017	0.017
2116	53*	0.116	4.57	4.57	4.50	4.49	4.48	0.016	0.017	0.017	0.018
2116	55	0.120	4.72	4.53	4.45	4.43	4.43	0.017	0.017	0.018	0.018
2116	58	0.130	5.12	4.45	4.38	4.36	4.36	0.017	0.018	0.018	0.018
3313	57	0.100	3.94	4.48	4.41	4.39	4.39	0.017	0.018	0.018	0.018
1080	65	0.072	2.83	4.29	4.21	4.19	4.18	0.019	0.019	0.019	0.020
1080	68	0.081	3.19	4.21	4.13	4.11	4.11	0.020	0.019	0.020	0.020
1080	70	0.087	3.43	4.16	4.08	4.05	4.05	0.020	0.019	0.020	0.020
106	73	0.050	1.97	4.09	4.01	3.97	3.97	0.020	0.020	0.020	0.020
106	78	0.063	2.14	3.97	3.89	3.83	3.83	0.02	0.021	0.020	0.022

Remark:
1) Test by SPDR method.
2) The data above show actual values and are not guaranteed, for your reference only.
3) RC* is not common type for reference.
4) Last update: Oct, 2025

Nevertheless, material-table values provide an engineering reference, but controlled-impedance production should use the material data and construction agreed for the actual PCB build.

Copper Weight and Finished Copper Thickness

Outer-layer finished copper may include base copper plus plated copper, while inner-layer copper is processed differently. Impedance modeling should therefore represent the finished conductor geometry as closely as practical.

Increasing copper thickness can also reduce fine trace/space capability and change the etched conductor profile. As a result, moving from 1 oz to 2 oz copper should be reviewed as a manufacturing change rather than treated as a simple material substitution.

When to Ask WellerPCB for a Custom 4-Layer Stackup

In general, a standard construction is often sufficient for general electronics, but custom stackup review is recommended for controlled impedance, RF routing, high-speed interfaces, 2 oz or heavier copper, unusual finished thickness, tight mechanical constraints, or special laminate requirements.

Send WellerPCB your Gerber files, fabrication drawing, target board thickness, copper requirements, and impedance table. Next, the engineering team can review the proposed construction before fabrication and recommend a manufacturable stackup.

Request a PCB Engineering Review →

Power Integrity and EMC in a 4-Layer PCB

Although a dedicated power plane simplifies distribution, PDN performance still depends on decoupling, via inductance, plane geometry, component placement, and current paths. Meanwhile, when L3 contains multiple power islands, check whether those splits affect signals routed on adjacent layers.

Finally, for EMC, keep high-speed signals close to continuous reference planes, minimize high-frequency current-loop area, avoid unnecessary plane slots, and provide appropriate return paths around signal-layer transitions.

Common 4-Layer PCB Stackup Mistakes

Choosing the stackup after routing: define the preliminary construction before critical routing and impedance work.
Assuming every 1.6 mm board has the same geometry: total thickness does not define signal-to-plane spacing.
Routing across plane splits: a broken return path can increase loop area and create SI or EMI problems.
Treating FR-4 as one fixed Dk: laminate system, glass style, resin content, frequency, and test method affect electrical properties.
Ignoring finished copper: plating changes conductor thickness and profile.
Forcing dense routing into four layers: additional layers can be preferable to sacrificing plane continuity or manufacturing margin.

4-Layer PCB Stackup Design Checklist

✓Identify controlled-impedance nets and target tolerances.

✓Assign continuous reference planes to critical signals.

✓Check return paths at vias and layer transitions.

✓Define finished board thickness and copper by layer.

✓Confirm prepreg/core construction and dielectric data.

✓Review trace/space capability against copper weight.

✓Check resin filling for heavy-copper constructions.

✓Confirm DFM, impedance coupon, and TDR requirements before production release.

4-Layer PCB Stackup FAQ

What is the most common 4-layer PCB stackup?

A common arrangement is Signal / Ground / Power / Signal. It gives top-layer routing a nearby ground reference and provides a practical starting point for many products.

Is a 4-layer PCB suitable for high-speed design?

Yes, when routing density, interfaces, and reference-plane requirements fit the available layer structure. Dense or demanding systems may need six or more layers.

Can a 4-layer PCB use 2 oz copper?

Yes. Heavier copper changes etching, trace/space capability, resin filling, lamination, and impedance geometry, so the construction should be reviewed before release.

How is 50Ω impedance determined on a 4-layer PCB?

Use the actual signal-to-reference dielectric height, finished copper thickness, trace width, material Dk, and relevant solder-mask model. Production calculations should use the approved stackup rather than nominal overall board thickness.

Should the PCB manufacturer approve the stackup before routing?

For controlled impedance, heavy copper, unusual thicknesses, or tight fabrication constraints, early stackup review is recommended because it reduces the risk of geometry changes after routing is complete.

Post Views: 136

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Lead free PCB assembly, PCB Stackup Design，4 Layer PCB，Impedance Control，Signal Integrity，Power Integrity，EMC Design，PCB Fabrication， High Speed PCB，Ground Planes，PCB Layout

By Jason Chu

A graduate in Automation Control, with 20+ years in PCB engineering, fabrication, assembly, and software/hardware testing. Handled projects for Fortune 500 companies such as IBM, Huawei, Samsung, Sony, Seagate, Schneider Electric and Toshiba, and brings extensive expertise in high-end electronics manufacturing.