PCB controlled impedance is the process of designing and manufacturing a PCB transmission line so its characteristic impedance stays within a specified target and tolerance. It is not determined by trace width alone. In practice, the result depends on conductor geometry, dielectric thickness, dielectric constant, reference-plane configuration, differential spacing, and the way the PCB is actually fabricated.
Therefore, for high-speed digital, RF, and other signal-integrity-sensitive designs, impedance control should be defined during stackup planning and verified after fabrication. A correct layout can still miss the target if the finished geometry or material properties differ from the model.
Controlled Impedance vs. Trace Resistance
Although characteristic impedance and DC resistance both use ohms, they describe different electrical behavior. By contrast, resistance describes conductor loss under current flow. Characteristic impedance describes the voltage-to-current relationship of a propagating wave in a transmission-line structure.
| Parameter | Controlled Impedance | DC Resistance |
|---|---|---|
| Purpose | Transmission-line behavior | Conductor loss |
| Key Variables | W, T, H, Dk, reference geometry | Length, width, thickness, resistivity |
| Reference Plane | Normally required | Not required |
| Verification | TDR / impedance measurement | Resistance measurement |
An impedance discontinuity can reflect signal energy and contribute to ringing, overshoot, timing uncertainty, or reduced eye opening. A low-resistance trace can therefore still be a poor high-speed transmission line.
What Determines PCB Trace Impedance?
The key parameters are coupled. As a result, changing one geometry or material variable can require another to change if the same target impedance must be maintained.
Trace Width, Copper Thickness, and Dielectric Height
In general, for a typical microstrip, increasing trace width or conductor thickness lowers impedance, while increasing the distance to the reference plane raises it. Trace width therefore cannot be finalized independently of the stackup.
Moreover, the Gerber width is not necessarily the final physical width. Etching, plating, and sidewall shape can change the manufactured conductor geometry.
Dielectric Constant and Material Construction
Likewise, a higher effective dielectric constant generally lowers impedance for the same geometry. However, “FR-4 Dk” is not one universal value; material system, resin content, glass style, frequency, and test method affect modeling. Therefore, use the laminate supplier’s design Dk or a fabricator-approved value where available. See WellerPCB’s prepreg Dk selection guide.
Differential-Pair Spacing
In addition, differential impedance depends on width, thickness, dielectric geometry, reference planes, and pair spacing. As a result, changing spacing changes coupling and can create local impedance variation even when trace width stays constant.
Common Controlled-Impedance Structures and Targets
Because different transmission-line structures place the conductor in different electromagnetic environments, the structure must be defined before the target geometry is calculated.
- Microstrip: an outer-layer trace referenced to a plane below it; solder mask may influence the model.
- Stripline: an internal trace embedded between reference planes, with fields more contained inside the dielectric.
- Embedded microstrip: an internal or partially embedded conductor with a primary reference-plane relationship.
- Coplanar waveguide: a trace that also couples to adjacent same-layer ground conductors, often with a reference plane below.
For a focused comparison, see stripline vs. microstrip.
For example, common nominal targets include 50Ω, 75Ω, 90Ω, and 100Ω, depending on the interface and system. These are examples, not universal PCB values; use the applicable interface specification.
How to Calculate PCB Controlled Impedance
In practice, impedance calculation should progress from a first-pass estimate to a model based on the actual stackup and production geometry. Therefore, the required method depends on the transmission-line structure, accuracy target, and manufacturing stage.
Use Analytical Equations for First-Pass Estimation
For example, a commonly used first-order microstrip approximation is:
Z₀ = 87 / √(εr + 1.41) × ln(5.98H / (0.8W + T))
- Z₀ = characteristic impedance
- H = dielectric height to the reference plane
- W = trace width
- T = trace thickness
- εr = relative dielectric constant
Engineering Boundary — First-Pass Formula Only
Use this equation for preliminary microstrip estimation, not final production modeling. Coplanar structures, asymmetric stackups, plated conductor profiles, solder mask, or tight impedance tolerances should be evaluated with the actual stackup and a suitable field solver.
Use a Field Solver for Production Geometry
For production work, tools such as Polar Instruments Si9000 can model dielectric thickness, Dk, conductor thickness, solder mask, differential spacing, and line structure. WellerPCB also provides a microstrip impedance calculator for initial estimation; production values should use the actual stackup and manufacturing assumptions.
50Ω Example: Calculated Geometry Is Not Final Geometry
50Ω Microstrip Example — First-Pass Inputs
| Target | 50Ω |
| Trace Width (W) | 0.20 mm |
| Copper Thickness (T) | 35 μm |
| Dielectric Height (H) | 0.15 mm |
| Example Dk | 4.2 |
Engineering boundary: these are model inputs, not guaranteed production dimensions.
However, these values support only a first-pass model, so the calculated width should not automatically become the production width. Therefore, the fabricator must account for laminate, final dielectric thickness, plated copper, etch compensation, conductor profile, solder mask, and process tolerance. The key distinction is calculated geometry versus manufactured geometry.
How Stackup and Manufacturing Shift Impedance
First, PCB stackup defines the reference planes, dielectric thicknesses, core and prepreg construction, copper thickness, and layer spacing that form the transmission line. By contrast, manufacturing determines how closely the finished board matches that model. See the multilayer PCB stackup design guide.
Lamination, Prepreg, and Dk
For example, prepreg does not necessarily finish at its nominal catalog thickness after lamination. Resin content, glass style, copper pattern, and lamination conditions influence final dielectric height. Therefore, review the actual material construction rather than treating prepreg thickness as fixed. See WellerPCB’s PCB base material selection guide.
Etching, Plating, and Solder Mask
In addition, etching changes final trace width and sidewall profile. In addition, outer-layer plating changes conductor thickness, while solder mask changes the dielectric environment around exposed microstrip structures. These effects become more important as impedance tolerance tightens.
Surface Roughness and High-Frequency Loss
Moreover, at higher frequencies, copper roughness affects conductor loss and can influence electrical behavior. For demanding RF and high-speed designs, evaluate roughness, laminate loss, Dk, and geometry together.
Differential Pairs and Reference Planes
Differential impedance depends on width, spacing, dielectric geometry, copper thickness, reference-plane relationship, and coupling. Accordingly, keep pair geometry consistent through the controlled section unless a transition has been intentionally modeled.
At the same time, the reference structure is equally important. Therefore, avoid routing controlled-impedance signals across split planes, large voids, slots, or abrupt reference changes. As a result, a return-path discontinuity can create an impedance discontinuity even when the signal trace width does not change.
Controlled-Impedance Manufacturing Workflow
A reliable process connects design intent to the actual fabricated structure and its measured result.
Controlled-Impedance Production Flow
- Define: target impedance, tolerance, signal layer, and reference plane.
- Build: stackup, material system, copper thickness, and dielectric geometry.
- Calculate: trace width and differential spacing using the intended structure.
- Review: etching, plating, lamination, and minimum-geometry capability.
- Adjust: width, spacing, dielectric thickness, or stackup where required.
- Fabricate: the PCB and representative impedance coupon.
- Measure: the coupon with TDR.
- Accept: compare the measured result with the defined target and tolerance.
Impedance Tuning
Stackup flexible: adjust width, spacing, dielectric height, material, or copper.
Stackup fixed: focus on width, spacing, and manufacturing compensation.
Geometry fixed: recheck feasibility before fabrication.
How Controlled Impedance Is Verified
Calculation defines the intended transmission line; measurement determines whether the fabricated structure meets the target and tolerance. Verification connects a representative coupon, TDR measurement, and a defined acceptance limit.
Impedance Coupon
An impedance coupon is fabricated with the production panel to represent the relevant transmission-line construction, including the signal layer, reference plane, dielectric construction, trace width, copper thickness, and differential spacing where applicable. See WellerPCB’s PCB impedance test coupon guide.
TDR Measurement and Evidence Boundary
Time Domain Reflectometry sends a fast transition through the test structure and evaluates reflections caused by impedance changes. The measured response is compared with the specified target and project-defined tolerance.
| Evidence | What It Confirms | What It Does Not Confirm |
|---|---|---|
| Field-Solver Model | Expected impedance for the modeled stackup and geometry | Actual fabricated geometry or production variation |
| Coupon + TDR | Manufactured transmission-line structure represented by the coupon | Every via, connector, plane transition, or local routing discontinuity |
| Board-Level SI Validation | Behavior of the tested interconnect under defined system conditions | Other layouts, revisions, stackups, or untested operating conditions |
Acceptance Boundary
Define impedance tolerance from the project requirement, interface specification, or controlled fabrication drawing. Do not assume ±10% is universal.
Why PCB Impedance Can Miss the Target
When measured impedance differs from target, troubleshoot the physical variables that changed between the model and manufactured board. The failure pattern can narrow the investigation to geometry, material, process, or reference-path effects.
| Observed Risk | Variables to Check |
|---|---|
| Impedance consistently high or low | Trace width, dielectric height, Dk, copper thickness |
| Differential result out of target | Pair spacing, width, reference geometry, coupling |
| Lot-to-lot drift | Lamination, etching, plating, material construction |
| Local discontinuity | Reference-plane changes, vias, connector transitions, routing geometry |
| Model and measurement disagree | Actual stackup, effective Dk, solder mask, conductor profile, test assumptions |
Manufacturing compensation is part of impedance control. A calculated CAD width transferred directly into production can miss the target if process effects are ignored.
PCB Controlled-Impedance Release Checklist
Before release, confirm that the electrical target, stackup assumptions, manufacturing controls, and verification requirements all describe the same intended transmission-line structure.
- Specify target impedance and tolerance.
- Identify single-ended or differential structures.
- Define signal and reference layers.
- Use the actual stackup, material, Dk, copper thickness, and dielectric height.
- Define differential spacing where applicable.
- Review solder mask and conductor-profile assumptions for external structures.
- Confirm etching, plating, and lamination capability with the fabricator.
- Include or approve a representative impedance coupon.
- Define TDR measurement and reporting requirements.
- Keep board-level discontinuity checks separate from coupon acceptance.
PCB Controlled Impedance FAQ
What is controlled impedance in PCB design?
It is the design and manufacturing control of a PCB transmission line so its characteristic impedance stays within a specified target and tolerance.
How do you calculate 50Ω PCB impedance?
Use the actual transmission-line structure, trace width, copper thickness, dielectric height, Dk, and reference geometry. Analytical equations are useful for estimation; production designs should use a suitable field solver and manufacturing stackup.
How is controlled impedance tested?
It is commonly verified by TDR measurement of a representative impedance coupon fabricated with the production panel
Why can fabricated impedance differ from the calculated value?
The finished board may differ from the model in trace width, copper thickness, dielectric height, Dk, solder mask, conductor profile, or other manufacturing variables.
